1. Field of the Invention
The present invention relates to the fabrication of integrated circuits, and, more particularly, to the implanting of ions of dopant materials into workpieces and/or substrates suitable for the fabrication of integrated circuits. More specifically, the present invention relates to a method of forming shallow “halo” structures of field effect transistors.
2. Description of the Related Art
In the last several years, the number of circuit elements manufactured on semiconductor substrates has continuously grown. For example, in modem integrated circuit devices, there may be approximately one billion elements per chip due to the continuing miniaturization of feature sizes.
Presently, circuit elements are commonly fabricated featuring minimal sizes of less than 0.18 μm and the progress in manufacturing technology seems likely to continue on in this manner. However, in the particular case of field effect transistors, with the increasing miniaturization of the transistors, it became apparent that MOSFETs exhibit short-channel effects not predicted by the standard MOSFET models. Such short-channel effects comprise, among others, sub-surface punch-through in NMOSFETs and punch-through in PMOSFETs.
Great efforts have been made and several measures have been taken to prevent short-channel MOSFETs from entering the punch-through regime. Among these measures, implanting dopants under the source/drain extension (SDE) regions has proved to be the most reliable and has, therefore, become the most likely used technique for preventing punch-through behavior in field effect transistors. Such implants have been termed “halo” implants.
However, in view of the reduced lateral dimensions of the transistors, the doping profiles of “halo” implants have to also be restricted to shallower locations, that is, “halo” implantations need to be confined within shallow regions close to the surface of the substrate on which the transistors have to be formed. To obtain the shallow halo doping profiles required for source/drain extensions and channels, all physical mechanisms allowing dopants to penetrate deeper into silicon must be strictly controlled or eliminated. In particular, the principal factor to be controlled is ion channeling. To accomplish this end, shallow profile halo doping processes often used a so-called “pre-amorphization” implantation step before the actual halo dopant implantation. In particular, an amorphous zone is usually formed during a first single pre-amorphization implantation and, during a subsequent implantation process (comprising either a single step or a plurality of steps), the doped regions (halo and source/drain extension regions) are formed. Normally, heavy inert ions like germanium or xenon are implanted at an implant energy of approximately 80-200 keV to fully amorphize the surface region of the substrate.
In the following, a description will be given with reference to FIGS. 1a-1d of a typical prior art process for forming the active regions of a field effect transistor, including a typical “pre-amorphization” implanting step as well as a typical “halo” implanting step.
FIG. 1a schematically shows a MOS transistor 100 to be formed on a substrate 1, such as a silicon wafer. Isolation structures 2 define an active region of the transistor 100. Moreover, reference 3 relates to a polysilicon gate electrode of the MOS transistor 100. Reference 6 denotes a gate insulation layer. Reference 7a relates to an ion beam to which the substrate 1 is exposed during a “pre-amorphization” implanting process, and reference 5a relates to amorphous regions formed into the substrate 1.
In FIGS. 1b-1d, those parts already described with reference to FIG. 1a are identified by the same reference numerals. In addition, in FIG. 1b, reference 7e relates to an ion beam to which the substrate 1 is exposed for forming the source/drain extension regions of the transistor 100. Moreover, references 5′S and 5′D relate to the source/extension region and the drain extension region, respectively, of the transistor 100.
FIG. 1c shows the MOS transistor 100 once halo regions 5h have been formed during a prior art halo implantation step. In particular, in FIG. 1c, references 7ha and 7hb relate to corresponding angled ion beams to which the substrate 1 is exposed for forming the halo regions 5h. The dopant material implanted during such a process is of the same type as the dopant used in doping the substrate. That is, the halo implants for NMOS and PMOS devices are performed using a P-type and an N-type dopant material, respectively. In a sense, the halo implants reinforce the dopants in the substrate.
In FIG. 1d, reference 4 relates to dielectric sidewall spacers formed on the sidewalls of the polysilicon line 3 and references 5S and 5D relate to the source and drain regions, respectively, after a further heavy implantation step has been carried out for determining the final concentration of dopants in the source and drain regions.
A typical process flow for forming the active regions of the transistor 100 comprising the amorphous regions 5a, the halo structures 5h, and the source and drain regions 5S and 5D may include the following steps.
Following the formation of the gate insulation layer 6 and the overlying polysilicon line 3 according to well-known lithography and etching techniques, the amorphous regions 5 are formed during a first step (see FIG. 1a) with a single pre-amorphization implantation. To this end, the substrate 1 is exposed to the ion beam 7a and heavy ions such as, for example, phosphorous, arsenic and argon are implanted into the substrate at an implanting energy of about 18 keV.
It has been observed that at a predefined implanting dose, local amorphous regions are created by the ions penetrating into the substrate, which eventually overlap as the implanting process is carried out until a continuous amorphous layer is formed.
This amorphous layer is formed with the purpose of controlling ion channeling during the next implanting steps so as to obtain shallow implanting profiles for both the halo regions and the source and drain regions to be formed in the substrate. That is, the implanted ions do not penetrate in an amorphous layer as deeply as in a crystalline layer so that the implanted ions can be confined to shallower regions and the actual doping profile and final dopant concentration of those regions implanted after the pre-amorphization implantation step can be better controlled.
In a next step, as depicted in FIG. 1b, a second ion implantation step is carried out to form the source/drain extension regions 5′S and 5′D. To this end, by exposing the substrate 1 to the ion beam 7e, a dose of approximately 3×1013-3×1014 cm−2 dopant ions is implanted at low energy (30-50 keV). The implantation process causes the edges of these implanted regions to be substantially aligned with the edge of the gate, i.e., this is a self-aligned process. The second ion .implantation step is performed with N-type and P-type dopant materials for NMOS and PMOS devices, respectively.
The halo regions 5h of the transistor 100 are then formed during a subsequent step, as depicted in FIG. 1c. In particular, a further ion implantation step is carried out during which the substrate 1 is exposed to the ion beams 7ha and 7hb. This halo implant is also self-aligned with the channel edges and dopants are placed beneath those dopants implanted into the SDE regions and at a depth which is less than the depth of the amorphous regions 5a. As depicted in FIG. 1c, during halo implants, the ion beams 7ha and 7hb are kept at a tilt angle of approximately 30 degrees with respect to the surface of the substrate 1. In particular, the implanting step is divided into two parts. During the first part, the substrate 1 is exposed to the ion beam 7ha and a dose corresponding to one-half of the final dose is implanted. Once the first part is completed, the substrate is rotated 180 degrees about an axis perpendicular to the surface of the substrate and again exposed to the ion beam 7hb. In FIG. 1c, two ion beams 7ha and 7hb have been depicted for clarity reasons. However, during the second part of the implanting process, the ion beam 7hb corresponds to the ion beam 7ha during the first part, with the only difference being that the substrate 1 is rotated 180 degrees once the first part of an implanting step is completed. The dopant concentration in the regions 5h, as well as the implant energy and the dopants, are selected depending on the type of transistor to be formed on the substrate 1. For instance, boron ions in NMOS and phosphorous in PMOS are implanted to form a halo punch-through suppression region in each device. Usually, phosphorous is implanted at 90 keV with a dose of 2×1013 cm−2 at 25 degrees tilt, in two segments, with the substrate rotated 180 degrees between the two segments. Similar procedures are used for implanting boron. A thermal treatment, such as an annealing step, is usually performed after the ion implantation step for diffusing dopants into the substrate.
During a subsequent step, the source and drain regions 5S and 5D of the transistor 100 are completed, as depicted in FIG. 1d. In particular, dielectric sidewall spacers 4 are formed on the sidewalls of the polysilicon line 3 according to well-known techniques, and a further heavy implantation step is carried out for implanting dopants into those regions of the substrate not covered by the polysilicon line and the sidewall spacers 4. At the end of the heavy implantation step, the source and drain regions 5S and 5D are formed to exhibit the desired dopant concentration. For NMOS and PMOS type devices, this heavy implantation step is performed using an N-type and a P-type dopant material, respectively. The manufacturing process is then continued to complete the transistor 100 according to techniques well known to those skilled in the art.
As stated above, the pre-amorphization implanting process as depicted in FIG. 1a is performed for the purpose of controlling the ion channeling during the subsequent implanting steps so as to obtain doping profiles for both the halo structures and the source and drain regions that are as shallow as required in view of the reduced lateral dimensions of the modern transistors. That is, by pre-amorphizing the substrate, the dopants implanted into the substrate during subsequent implanting processes are confined to shallow regions of a reduced depth close to the surface of the substrate, with these shallow regions exhibiting a well-defined dopant concentration and reduced junction depth.
However, the prior art pre-amorphization process as depicted with reference to FIG. 1a is quite troublesome and time-consuming. In fact, heavy ions have to be implanted and the implantation is performed during a time that is long enough to allow crystal damage induced by the implanted ions to accumulate so as to form a continuous amorphous layer. In particular, the long implantation time required results in a negative impact on the productivity and in increased production costs. Moreover, implanting equipment on a large scale is required, which also results in higher production costs.
Accordingly, in view of the problems explained above, it would be desirable to provide a technique that may solve or at least reduce one or more of these problems. In particular, it would be desirable to provide a technique that allows the prevention and/or reduction of ion channeling during halo implantation and source and drain implantation processes.